Instantiate System Verilog into a VHDL Testbench

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The answer depends on your simulator features; Modelsim-ASE is a single-language simulator, so it can only simulate VHDL or SystemVerilog, not both at the same time.

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Dave,

this link seems to indicate that modelsim- altera starter edition is mixed-language ...? (https://www.altera.com/products/design-software/model---simulation/modelsim-altera-software.html) :

starting with quartus software v15.0, the modelsim-altera edition software supports dual-language simulation. this includes designs that are written in a combination of verilog, system verilog, and vhdl languages, also known as mixed hdl.

Regards,

Josy