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Altera_Forum
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10 years ago

Instantiate System Verilog into a VHDL Testbench

Good Evening, I am currently working on a project for school where we taking the original concepts we learned in VHDL and applying them to build the same components with System Verilog. I alrea...
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Altera_Forum
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10 years ago

Hi Josy,

Thanks for that reference, I didn't know that Altera had changed the tool to support both languages ... I guess they got sick of trying to figure out how to simulate their new SystemVerilog IP with VHDL in a single-language simulator and this was the easiest way to solve that problem! :)

Cheers,

Dave