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Altera_Forum

Honored Contributor

16 years ago

incmprehensible error

Hi !!

When i compile my programm, I have these errors :

--- Quote Start ---

Error: Can't pack LABs

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[0]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~397" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[1]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~401" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[2]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[3]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~405" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[4]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~409" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[5]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~413" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[6]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|_~417" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[7]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[8]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[9]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[10]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[11]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[12]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[13]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[14]" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[0]~292" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[0]~296" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[1]~302" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[1]~307" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[2]~313" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[2]~318" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[3]~324" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[3]~329" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[4]~335" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[4]~340" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[5]~346" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[5]~351" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[6]~357" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[6]~362" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[7]~368" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[7]~373" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[8]~379" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[9]~385" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[10]~391" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[10]~393" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[11]~399" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[12]~403" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[13]~409" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[14]~412" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[3]~422" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[0]~124bal" of type max_mcell

Error: Can't place node "lpm_counter:control_2_rtl_0|dffs[0]~125bal" of type max_mcell

Error: Can't find fit

Error: Quartus II Fitter was unsuccessful. 50 errors, 5 warnings

Error: Peak virtual memory: 149 megabytes

Error: Processing ended: Mon Nov 15 21:38:29 2010

Error: Elapsed time: 00:00:05

Error: Total CPU time (on all processors): 00:00:04

Error: Quartus II Full Compilation was unsuccessful. 52 errors, 14 warnings

--- Quote End ---

My programm consists to a variable control_2 (std_logic_vector (15 downto 0)) which count up to a constant value . When this value is egal, control_2 is initialized to 0 and count up a new time, etc...

The constant can be 4 values defined by the position of a commutator (hardware).

Here I don't understand all these errors, and more even if my constant et control_2 is always 16 bits, sometimes i don't have these errors sometimes i have. It depends the value of the constant.

An exemple :

--- Quote Start ---

divide_2 <= "11101010011000000" when choix_frequence = "0001" -- 8Hz

else "011000011010100" when choix_frequence = "0010" -- 80Hz

else "000010011100010" when choix_frequence = "0100" -- 800Hz

else "000000001111101" when choix_frequence = "1000" -- 8000Hz

else "000000000000001";

--- Quote End ---

Here divide_2 is the constant. The values of divide_2 generate or not the compilation errors.

Why if for 8000Hz my value is "000000001101101" I have these errors?

And why for this case if my value is "000000001111101" I don't have errors...? The compilation is ok and my outpout is ok.

Please Help me...:confused:

15 Replies

Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Hi !!

When i compile my programm, I have these errors :

My programm consists to a variable control_2 (std_logic_vector (15 downto 0)) which count up to a constant value . When this value is egal, control_2 is initialized to 0 and count up a new time, etc...

The constant can be 4 values defined by the position of a commutator (hardware).

Here I don't understand all these errors, and more even if my constant et control_2 is always 16 bits, sometimes i don't have these errors sometimes i have. It depends the value of the constant.

An exemple :
Here divide_2 is the constant. The values of divide_2 generate or not the compilation errors.

Why if for 8000Hz my value is "000000001101101" I have these errors?
And why for this case if my value is "000000001111101" I don't have errors...? The compilation is ok and my outpout is ok.

Please Help me...:confused:
--- Quote End ---

Hi,

your post is also a little bit confusing. You posted that your compilation isn't successful, but later on you wrote that the compilation and your output is ok ?

BTW: What is the width of your signal, 16 bit ? You compare values are 17 bit or 15 bit ???

11101010011000000 17 bit
011000011010100 15 bit
000010011100010
000000001111101
000000000000001

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Sorry for my confusing post.

What I mean, all variables were created with the same bit number. I tested with 15, 16 and 17 bits, I have the same problem.

For a gived value, I was a compilation problem. For another value (same bit number) i have a compilation problem.

pletz (http://www.alteraforum.com/forum/member.php?u=1380) => sorry I mixed two test programms for my example.

To resume : for the 80Hz value the compilation is ok for "111" but not ok for "101". (It's an example, the true problem appears with a 16 bit signal std_logic_vector).
Altera_Forum
Honored Contributor
16 years ago
Hi,
Your design is too big to your device. You reach the limits.
it is not a logic problem (in that case :-) ) , the Qaurtus fitter said that it can not fit (place) your design.
Altera_Forum
Honored Contributor
16 years ago
But what i don't undertsand is : why with some values we have some problems and with others I have no problem?

With 16 bits (0 to 65 535) i can have some compilation problems with the value 35500 but not with 40000 (for an example) or 35501 or 20000... I search the reason of this problem. We have some problems with a type of number? I can't have '1' with the 10th bit etc...

Thank you for your help ;)
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
But what i don't undertsand is : why with some values we have some problems and with others I have no problem?

With 16 bits (0 to 65 535) i can have some compilation problems with the value 35500 but not with 40000 (for an example) or 35501 or 20000... I search the reason of this problem. We have some problems with a type of number? I can't have '1' with the 10th bit etc...

Thank you for your help ;)
--- Quote End ---

Hi,

is it possible for you to post your source code or could you attach your Quartus project ?

Kind regards

GPK
Altera_Forum
Honored Contributor
16 years ago
Best to post the whole project indeed - it may simply be that the device is full or so. You can't see that from the source code.

BR,

Ben
Altera_Forum
Honored Contributor
16 years ago
you may try to use down-counter : which counts from divide_2 downto 0.
It is easier to compare a std_logic_vector with 0. The logical comparison is obvious and it needs just some OR gates.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
you may try to use down-counter : which counts from divide_2 downto 0.
It is easier to compare a std_logic_vector with 0. The logical comparison is obvious and it needs just some OR gates.
--- Quote End ---

Not exactly so. What you gain on the swings you loose on the roundabouts.
Let's say we have a counter and we have to count X, with X being dynamical.
If we count up, we must clear the counter to zero and compare the count to X
Clearing is (or can be) cheap, comparing uses a 2-tier of XORs and AND
If we count down, we must load the value X into the counter, and compare the count with 0.
Loading the counter needs an additional multiplexer at the counter's input, but has a simpler comparison with a single AND. It may be possible that we could make the count loading simpler, but I have to try that out (in my free time?).
Altera_Forum
Honored Contributor
16 years ago
all variables are std_logic or std_logic_vector

My VHDL programm is (for an EPM3064ALC44-10)

--- Quote Start ---
architecture DESCRIPTION of test_impulsion is
signal divide_2 : std_logic_vector (16 downto 0):= "00000000000000000";
signal control_2 : std_logic_vector (16 downto 0):= "00000000000000000";
signal choix_frequence : std_logic_vector (3 downto 0);
signal choix_sonde : std_logic_vector (3 downto 0);
signal sortie_sonde : std_logic_vector (4 downto 0);

begin

--
choix_frequence (0) <= entree_40;
choix_frequence (1) <= entree_41;
choix_frequence (2) <= entree_39;
choix_frequence (3) <= entree_37;

--:D!! The problem is here, when I change one value, for 80Hz for an example
-- the value here is ""00010111011111000"", if I change one bit, maybe the
-- compilation is ok or not. Why? The error message is in ma first post:D!!

divide_2 <= "11100111100011000" when choix_frequence = "0001" -- 8Hz
else "00010111011111000" when choix_frequence = "0010" -- 80Hz
else "00000010010011100" when choix_frequence = "0100" -- 800Hz
else "00000000001110110" when choix_frequence = "1000" -- 8000Hz
else "00000000000000001";

process (clk_43)
begin
if (clk_43'event and clk_43 ='1') then
if control_2 < divide_2 then
control_2 <= control_2+"00000000000000001";
elsif control_2 = divide_2 then
control_2 <= "00000000000000000";
elsif control_2 > divide_2 then
control_2 <= "00000000000000000";
else control_2 <= control_2;
end if;
end if;
end process;

process (control_2)
begin
If (control_2 = 0 or control_2 = 1 or control_2 =2) then
sortie_11 <='1';
else sortie_11 <='0';
end if;
end process;

sortie_28 <= entree_34;
sortie_26 <= entree_33;
sortie_24 <= entree_31;
sortie_27 <= entree_29;

choix_sonde(0)<= entree_29;
choix_sonde(1) <= entree_31;
choix_sonde(2) <= entree_33;
choix_sonde(3) <= entree_34;

sortie_sonde <= "10010" when choix_sonde = "1000" -- sonde SA70-2
else "10110" when choix_sonde = "0100" -- sonde SBM-2D
else "10111" when choix_sonde = "0010" -- sonde SBG
else "11001" when choix_sonde = "0001" -- SG-2
else "00000";

sortie_4 <= sortie_sonde(4);
sortie_5 <= sortie_sonde(3);
sortie_6 <= sortie_sonde(2);
sortie_8 <= sortie_sonde(1);
sortie_9 <= sortie_sonde(0);

end DESCRIPTION;
--- Quote End ---
To describe the programm :
- entree_XX => input of the MAX3064
-output_XX => output of the MAX3064
==> XX is the pin number. All input and output are std_logic.
Hard clock : 1Mhz (quartz)

Choix_frequence => this value define the frequency
divide_2 => load the counter number
control_2 => the counter. When control_2 = divide_2,control_2 begin a new counter since 0.

The output is a 3us pulse, so 3 countings of control_2 (when control_2 is 1, 2, and 3 my output is '1', others values output is '0').

edit :
total macrocells : 54/64(84%)
Altera_Forum
Honored Contributor
16 years ago
I guess you use ieee.std_logic_unsigned.all; ? you and others might have a look at http://www.velocityreviews.com/forums/showpost.php?p=142537&postcount=3
process (clk_43) begin if (clk_43'event and clk_43 ='1') then if control_2 < divide_2 then control_2 <= control_2+"00000000000000001"; elsif control_2 >= divide_2 then -- modified here control_2 <= "00000000000000000"; else control_2 <= control_2; end if; end if; end process;

Your process(control_2) needs huge resources : 3 comparisons. Synthesis are still "stupid" and you have to "help" their work.
I suggest you to employ something like
sortie_11 <= '1' when control_2 <= 3 else '0';

better is using a process(clk) which avoids glitches of control_2. (It takes only one more D Flip Flop)

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incmprehensible error

15 Replies

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