incmprehensible error

all variables are std_logic or std_logic_vector

My VHDL programm is (for an EPM3064ALC44-10)

--- Quote Start ---

architecture DESCRIPTION of test_impulsion is

signal divide_2 : std_logic_vector (16 downto 0):= "00000000000000000";

signal control_2 : std_logic_vector (16 downto 0):= "00000000000000000";

signal choix_frequence : std_logic_vector (3 downto 0);

signal choix_sonde : std_logic_vector (3 downto 0);

signal sortie_sonde : std_logic_vector (4 downto 0);

begin

--

choix_frequence (0) <= entree_40;

choix_frequence (1) <= entree_41;

choix_frequence (2) <= entree_39;

choix_frequence (3) <= entree_37;

--:D!! The problem is here, when I change one value, for 80Hz for an example

-- the value here is ""00010111011111000"", if I change one bit, maybe the

-- compilation is ok or not. Why? The error message is in ma first post:D!!

divide_2 <= "11100111100011000" when choix_frequence = "0001" -- 8Hz

else "00010111011111000" when choix_frequence = "0010" -- 80Hz

else "00000010010011100" when choix_frequence = "0100" -- 800Hz

else "00000000001110110" when choix_frequence = "1000" -- 8000Hz

else "00000000000000001";

process (clk_43)

begin

if (clk_43'event and clk_43 ='1') then

if control_2 < divide_2 then

control_2 <= control_2+"00000000000000001";

elsif control_2 = divide_2 then

control_2 <= "00000000000000000";

elsif control_2 > divide_2 then

control_2 <= "00000000000000000";

else control_2 <= control_2;

end if;

end if;

end process;

process (control_2)

begin

If (control_2 = 0 or control_2 = 1 or control_2 =2) then

sortie_11 <='1';

else sortie_11 <='0';

end if;

end process;

sortie_28 <= entree_34;

sortie_26 <= entree_33;

sortie_24 <= entree_31;

sortie_27 <= entree_29;

choix_sonde(0)<= entree_29;

choix_sonde(1) <= entree_31;

choix_sonde(2) <= entree_33;

choix_sonde(3) <= entree_34;

sortie_sonde <= "10010" when choix_sonde = "1000" -- sonde SA70-2

else "10110" when choix_sonde = "0100" -- sonde SBM-2D

else "10111" when choix_sonde = "0010" -- sonde SBG

else "11001" when choix_sonde = "0001" -- SG-2

else "00000";

sortie_4 <= sortie_sonde(4);

sortie_5 <= sortie_sonde(3);

sortie_6 <= sortie_sonde(2);

sortie_8 <= sortie_sonde(1);

sortie_9 <= sortie_sonde(0);

end DESCRIPTION;

--- Quote End ---

To describe the programm :

- entree_XX => input of the MAX3064

-output_XX => output of the MAX3064

==> XX is the pin number. All input and output are std_logic.

Hard clock : 1Mhz (quartz)

Choix_frequence => this value define the frequency

divide_2 => load the counter number

control_2 => the counter. When control_2 = divide_2,control_2 begin a new counter since 0.

The output is a 3us pulse, so 3 countings of control_2 (when control_2 is 1, 2, and 3 my output is '1', others values output is '0').

edit :

total macrocells : 54/64(84%)