incmprehensible error

I guess you use ieee.std_logic_unsigned.all; ? you and others might have a look at http://www.velocityreviews.com/forums/showpost.php?p=142537&postcount=3

process (clk_43)
begin
if (clk_43'event and clk_43 ='1') then
   if control_2 < divide_2 then
      control_2 <= control_2+"00000000000000001";
   elsif control_2 >= divide_2 then -- modified here
      control_2 <= "00000000000000000"; 
   else 
      control_2 <= control_2;
   end if;
end if;
end process;

Your process(control_2) needs huge resources : 3 comparisons. Synthesis are still "stupid" and you have to "help" their work.

I suggest you to employ something like

sortie_11 <= '1' when control_2 <= 3 else '0';

better is using a process(clk) which avoids glitches of control_2. (It takes only one more D Flip Flop)