Forum Discussion
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone,
I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA. Can anyone help me with that? Thanks in advance Modellpilot23 Replies
Altera_ForumHello Again,
Is it possible to erase the used CAM completely for re-use?- Altera_Forum
Yes. it compiles by assigning the generics to the values from your code. Still wondering how you came up with these values. And about your code for CAM, the depth is 128 and the data bits is 16. I have just changed the width to 8 to have a 128 bytes of data.
--- Quote Start --- It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling? If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer. --- Quote End --- - Altera_Forum
It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling?
If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer. - Altera_Forum
Hi,
I am new to this and I have a query. Is this code valid for cyclone 4 too? I am not having altsyncram option in here. I have a M9k block and need a CAM of 128 bytes memory with 8 bits of data and 8 bits of address. Thanks --- Quote Start --- An M9K can do a 32x8 CAM, so you'll basically change the parameters in M9K_CAM.vhd to do a 32x16 CAM(it needs to be a multiple of these dimensions), and then just tie off the extra ports. I built this quickly but believe it is correct. There is a presentation that is very old on this topic(it was done as Stratix was rolling out). I have a document that refers to it, so together you can use them for understanding. (Not the most professional delivery, but hey, if it works.) You can also just use the M9K_CAM.vhd and M9K.vhd files and just play with it yourself. --- Quote End --- - Altera_Forum
With FOR loop times from 2048 to 4096, the PC can not synthesize, out of memory in module quartus_map.exe
May be the numbers of loop is too larger to synthesize
- Altera_Forum
What happened when you tried it? If the base M9K makes a 32x8 CAM, then the depth and width look like multiples, so I see no problem. Although I think it's going to take 256 M9Ks to get that, so it will use a lot of resources.
- Altera_Forum
Dear Rysc,
Can your Parameterized_CAM be configured to parameter NUM_WORDS = 4096; parameter WRADDR_WIDTH = 12; parameter WIDTH = 16; or not ? - Altera_Forum
I have created a Verilog parameterized CAM that you may find useful. I'll attach it here. It is a Quartus II archive file that contains a simulation environment in the sim directory, and some documentation in the doc directory.
- Altera_Forum
Do you have parameterized_cam in Verilog code?
- Altera_Forum
The HDL is parameterized, so just put that in. I believe a 64x64 will require 16 M9Ks(x2 to get the width and x8 to get the depth). That should be do-able.
