Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
Altera_ForumHonored Contributor
Honored ContributorWith FOR loop times from 2048 to 4096, the PC can not synthesize, out of memory in module quartus_map.exe
May be the numbers of loop is too larger to synthesize
