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Altera_Forum
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18 years ago

Implementing CAM (Content Addressable Memory) on Cyclone III

Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
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Altera_Forum
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15 years ago

The HDL is parameterized, so just put that in. I believe a 64x64 will require 16 M9Ks(x2 to get the width and x8 to get the depth). That should be do-able.