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Altera_Forum
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18 years ago

Implementing CAM (Content Addressable Memory) on Cyclone III

Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
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Altera_Forum
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15 years ago

I have created a Verilog parameterized CAM that you may find useful. I'll attach it here. It is a Quartus II archive file that contains a simulation environment in the sim directory, and some documentation in the doc directory.