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Altera_Forum
Honored Contributor
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
Altera_ForumHonored Contributor
Honored ContributorIt should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling?
If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer.
