Seadog
Occasional Contributor
3 years agoIgnored create_clock warning in C V design
I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that reference clock; the .sdc file for the EMIF core also has a create_clock command for the same clock (referenced as pll_ref_clk per the port name on the EMIF top level).
Quartus is giving me the following warning:
Warning (332049): Ignored create_clock at ddr3_v20_p0.sdc(264): Incorrect assignment for clock. Source node: clkinbot_p already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.
Should I:
- comment out the create_clock command in the project .sdc file
- use the -add option (not sure why I would; the clock is routed to only one place)
- ignore the warning
Thanks.