Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorIgnored create_clock warning in C V design
I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that ...
SeadogOccasional Contributor
Occasional ContributorThe design is fully constrained, other than the parts I purposely did not constrain (it's on an eval board with a bunch of I/Os not really being used). And certainly the EMIF core is constrained.
