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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Ignored create_clock warning in C V design

I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that ...
Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

The design is fully constrained, other than the parts I purposely did not constrain (it's on an eval board with a bunch of I/Os not really being used). And certainly the EMIF core is constrained.