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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Ignored create_clock warning in C V design

I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

You can either ignore the warning or remove your create_clock command since, as you say, the clock is not being used anywhere else in your design. Does the tool still show the design as fully constrained?