Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorIgnored create_clock warning in C V design
I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that ...
sstrell
Super Contributor
Super ContributorYou can either ignore the warning or remove your create_clock command since, as you say, the clock is not being used anywhere else in your design. Does the tool still show the design as fully constrained?
