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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Ignored create_clock warning in C V design

I have a Cyclone V design with a DDR 3 controller. The reference clock for the DDR3 EMIF core is routed directly from a clock pin. The .sdc file for the project has a create_clock command for that ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.