Honored ContributorIf I use only FPGA part of Cyclone V SE device, the HPS is in reset state with CPU0 and CPU1 or I should load code to sleep CPU1?
And if HPS is not used the default frequency is 800 MHz? Should I load code to slow down CPU to save energy? Thanks
Honored ContributorHonored ContributorHmm, what about the preloader then ?
Honored Contributorif that so... should just using cyclone IV board instead... as not utilizing the nice SOC block in the cyclone V :D
Honored ContributorI see, the original post was for a dual core CycV :) We have only a single core CycV and fusing its reset line would ultimatively disable the preloader :) And yes, this IS crazy :D But we have economical reasons to re-use a certain COM that we obtain in high volumes, and that one has a CycV HPS we just don't need.
I put a while(1) { __asm__("WFE"); } into the HPSs kernel code now, as a first step.Honored ContributorThis post is kinda going in different directions. The original post was whether someone can purchase a board with an SoC device and not bother using the HPS and use the FPGA fabric and the answer is yes you can.
You could probably get away with not even tying off the HPS reset but the boot rom code will attempt to boot up the HPS in that case and it might consume more power that way. If that's no concern then you can simply design the FPGA user design as you normally would and simply not instantiate the HPS block in Quartus. If you want to put the HPS into a lower power state then I think enabling the cold reset port into the FPGA fabric and driving that in should have more power savings than having the CPU execute the WFE instruction. That cold reset will fanout to everything inside the HPS and hold them idle instead of just the CPU.Honored ContributorThanks for clarifying, now I begin to understand, then we have the same use-case as flz47655. Indeed we want to use only the FPGA part to save power (in our case: to avoid heat).
Our FPGA engineers (I'm from software), however, told me that a CycloneV can't be started up without the pre-loader - which is HPS software off course. Is this true ? Or can everything, that is normally done by the pre-loader, also be done in a different way ? This would be really awesome because it would make things much easier for us. Thanks a lot.Honored ContributorI talked to our FPGA engineer and he explained me that we're using Loans (HPS pins offered to the FPGA), and a precursor for a Loan is the pre-loader.
This answers my original question "what about the preloader". Sorry for polluting the forum a bit, I should have talked more to our FPGA engineer right away ... Thanks, RoelofHonored ContributorThat's correct, it's a chicken and egg problem where the HPS needs to configure it's I/O so that they can be loaned out to the FPGA. Unfortunately there is no other way to do this because their are muxes built into the HPS that rewire the I/O over to the FPGA fabric and the HPS doesn't become accessible for you to make those changes until the preloader is run.
Honored Contributor
