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If I use only FPGA part of Cyclone V SE device, the HPS is in reset state with CPU0 and CPU1 or I should load code to sleep CPU1?
And if HPS is not used the default frequency is 800 MHz? Should I load code to slow down CPU to save energy?
Thanks
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If you want to use FPGA only then you can just hold the HPS in reset since it has a dedicated pair of warm and cold resets. This will prevent it from trying to boot and setup it's PLLs. If those reset pins are not easily accessible on the board I guess an alternative would be to instantiate the HPS in your design, turn off all the interfaces except the cold reset from the FPGA, then just hardwire that reset in your user design.
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