how tooutput a high speed clock

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One option is to use a direct digital synthesizer (DDS). Analog devices has many devices."

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If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.

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"The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.

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I think is a solution about this.I thougt it before.I can just change the write cloclk of FIFO with timing sampling( don't know how to use digital filter to realize it). However, how can I control it when using equivalent sampling.

Yes you are right, I have a sample-and-hold in front of ADC.So ADC is not a problem. My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!

I am grateful for your help!

Thank you very much!

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If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.

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It all comes down to how low you can get the clock jitter. The dividers in a DDS are designed with low-jitter in mind.

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I have a sample-and-hold in front of ADC.So ADC is not a problem.

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How is the clock to the sample-and-hold generated? If it is from the FPGA, then you need to have very low sampling jitter.

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My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).

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The digital control is not complex; it is the triggering that is complex.

For the digital control, you would generate a 200MHz time-base, and then decide how often to sample. If you sample every 199 clocks, then the sampling frequency is ~1MHz and the sampling location relative to a 200 period 1MHz signal is 1 clock earlier, if you sample every 201 clocks, then the sampling location is 1 clock later. After 200 samples, you will have a full period at 200MHz and you can reconstruct your signal.

This will of only work if you have a trigger to start the sampling at exactly the same instant every time. Oh yeah. the trigger needs to have low jitter ...

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Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!

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You have not explained what is 'bad' about your FPGA output clock. Could you perhaps describe what you have done, or show a circuit diagram, and maybe post an oscilloscope trace.

Cheers,

Dave

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This will of only work if you have a trigger to start the sampling at exactly the same instant every time. Oh yeah. the trigger needs to have low jitter ...

I don't know why I need a trigger to start the sampling. I think I just need to count(assume the count value is N) in a period of the signal by 200M clock to get the period.Sample one point per N+1 cycle,and then I can get a 200M equivalent sampling rate(If I use 100M clock ,I can get a 100M equivalent).

The trigger is a problem.Because I need to measure the period of signal(as I mentioned before,counting in a period of the signal by 200M clock ). I can't adjust the signal to a square wave with a low jitter. It confused me for a long time.

Your intentions to build an equivalent sampling system have been wll understood. But the doubt was about the sample-and-hold bandwidth and aperture uncertainty of your ADC. The latter would also decide, if it's reasonable to generate the ADC sample clock inside the FPGA.

Related to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit.

P.S.: A more continuous phase interpolation beyond the capabilities of the digital DDS part can be achieved with the PLL dynamic phase shifting feature of newer FPGAs,

Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips.

But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system.

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I don't know why I need a trigger to start the sampling.

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Create a picture of a 3MHz sinusoid sampled at 200MHz. Now draw your 1MHz samples on that picture.

The naive thing to do, would be to draw the ~1MHz samples so that they accumulate next to each other on top of the 200MHz samples of the 3MHz sinusoid. This makes the unlikely assumption that your sinusoid is phase-locked to your FPGA clock and that you already know the input signal period.

Now draw 200 3MHz sinusoids with random phase.

Now how do you collect N-samples from these sinusoids and reconstruct the sinusoid? The answer is the trigger. For example, lets say your trigger can detect the zero crossing of the sinusoid, then that zero crossing event gives your repetitive sampling a reference point from which to capture samples; the 200MHz effective sampling rate is the reconstruction of N-samples spaced in time 1/200MHz apart relative to the trigger position.

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I think I just need to count(assume the count value is N) in a period of the signal by 200M clock to get the period.Sample one point per N+1 cycle,and then I can get a 200M equivalent sampling rate(If I use 100M clock ,I can get a 100M equivalent).

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Unless the signal you are looking at is the same each time, you will just be sampling random parts of the incoming waveform.

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The trigger is a problem.Because I need to measure the period of signal(as I mentioned before,counting in a period of the signal by 200M clock ). I can't adjust the signal to a square wave with a low jitter. It confused me for a long time.

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You are creating more problems by trying to solve this problem with an interlaced sampling scheme.

Cheers,

Dave

I think you are talking about random sampling, so it need the trigger. But I use the sequence sampling(I think random sampling is harder than sequence sampling). I just need one trigger (or a reset ) to start the sampling, while needn't trigger at every sample point.

First,I get the count value of one period of signal(count at main clock).Then, I sampling one point per N+1 cycles. I don't know that it is good method or not .

I am very confused at the signal processing of FPGA(include the input signal and output signal,as I said before the output signal wave is bad and FPAG need low jitter input signal).

Do you have any idea to deal with the problem.

Related to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit.

Does the output clock become good if I use the PLL of FPGA?

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Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips.

DDS chips output sinusoid.How can I use it to derive ADC?(add a compator?)

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But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system.

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I don't understand the jitter of ADC. I think the if the clock isn't beyond the maximum frenquency,the ADC can work properly.