how tooutput a high speed clock

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If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.

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It all comes down to how low you can get the clock jitter. The dividers in a DDS are designed with low-jitter in mind.

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I have a sample-and-hold in front of ADC.So ADC is not a problem.

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How is the clock to the sample-and-hold generated? If it is from the FPGA, then you need to have very low sampling jitter.

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My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).

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The digital control is not complex; it is the triggering that is complex.

For the digital control, you would generate a 200MHz time-base, and then decide how often to sample. If you sample every 199 clocks, then the sampling frequency is ~1MHz and the sampling location relative to a 200 period 1MHz signal is 1 clock earlier, if you sample every 201 clocks, then the sampling location is 1 clock later. After 200 samples, you will have a full period at 200MHz and you can reconstruct your signal.

This will of only work if you have a trigger to start the sampling at exactly the same instant every time. Oh yeah. the trigger needs to have low jitter ...

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Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!

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You have not explained what is 'bad' about your FPGA output clock. Could you perhaps describe what you have done, or show a circuit diagram, and maybe post an oscilloscope trace.

Cheers,

Dave