how tooutput a high speed clock

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One option is to use a direct digital synthesizer (DDS). Analog devices has many devices."

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If I can use a DDS,why can I use FPGA. I know we can use FPGA make a DDS.

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"The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.

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I think is a solution about this.I thougt it before.I can just change the write cloclk of FIFO with timing sampling( don't know how to use digital filter to realize it). However, how can I control it when using equivalent sampling.

Yes you are right, I have a sample-and-hold in front of ADC.So ADC is not a problem. My problem is I need control the clock to change the the sampling rate.If the signal in the low frenquecy,I just need change the frequency of clock. while in the high frenquecy,I need use equivalent sampling (it's need complex control so that create equivalent sampling pluse).Now I can create the right sampling pluse with FPGA, but the pluse output from FPGA is bad,so that ADC is not work properly!

I am grateful for your help!

Thank you very much!