Altera_Forum
Honored Contributor
Honored Contributorhow tooutput a high speed clock
I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work. thank you very much
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Altera_ForumHonored Contributor
Honored ContributorI think you are talking about random sampling, so it need the trigger. But I use the sequence sampling(I think random sampling is harder than sequence sampling). I just need one trigger (or a reset ) to start the sampling, while needn't trigger at every sample point.
First,I get the count value of one period of signal(count at main clock).Then, I sampling one point per N+1 cycles. I don't know that it is good method or not . I am very confused at the signal processing of FPGA(include the input signal and output signal,as I said before the output signal wave is bad and FPAG need low jitter input signal). Do you have any idea to deal with the problem.
