how tooutput a high speed clock

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I don't know why I need a trigger to start the sampling.

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Create a picture of a 3MHz sinusoid sampled at 200MHz. Now draw your 1MHz samples on that picture.

The naive thing to do, would be to draw the ~1MHz samples so that they accumulate next to each other on top of the 200MHz samples of the 3MHz sinusoid. This makes the unlikely assumption that your sinusoid is phase-locked to your FPGA clock and that you already know the input signal period.

Now draw 200 3MHz sinusoids with random phase.

Now how do you collect N-samples from these sinusoids and reconstruct the sinusoid? The answer is the trigger. For example, lets say your trigger can detect the zero crossing of the sinusoid, then that zero crossing event gives your repetitive sampling a reference point from which to capture samples; the 200MHz effective sampling rate is the reconstruction of N-samples spaced in time 1/200MHz apart relative to the trigger position.

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I think I just need to count(assume the count value is N) in a period of the signal by 200M clock to get the period.Sample one point per N+1 cycle,and then I can get a 200M equivalent sampling rate(If I use 100M clock ,I can get a 100M equivalent).

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Unless the signal you are looking at is the same each time, you will just be sampling random parts of the incoming waveform.

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The trigger is a problem.Because I need to measure the period of signal(as I mentioned before,counting in a period of the signal by 200M clock ). I can't adjust the signal to a square wave with a low jitter. It confused me for a long time.

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You are creating more problems by trying to solve this problem with an interlaced sampling scheme.

Cheers,

Dave