Altera_Forum
Honored Contributor
Honored Contributorhow tooutput a high speed clock
I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work. thank you very much
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorYour intentions to build an equivalent sampling system have been wll understood. But the doubt was about the sample-and-hold bandwidth and aperture uncertainty of your ADC. The latter would also decide, if it's reasonable to generate the ADC sample clock inside the FPGA.
Related to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit. P.S.: A more continuous phase interpolation beyond the capabilities of the digital DDS part can be achieved with the PLL dynamic phase shifting feature of newer FPGAs, Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips. But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system.
