Altera_Forum
Honored Contributor
Honored Contributorhow tooutput a high speed clock
I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work. thank you very much
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorRelated to the jitter performance of high speed ADC, the FPGA clock tree is not so good, but I guess, it can keep with your 1 MHz ADC respectively the involved S/H circuit.
Does the output clock become good if I use the PLL of FPGA? ======================= Another option is to derive the sample event from an analog interpolated DDS signal, as e.g. provided by the Analog Devices DDS chips. DDS chips output sinusoid.How can I use it to derive ADC?(add a compator?) ========================= But I didn't yet hear about the aperture jitter of your ADC which is the basic hardware limitation for the system. --- Quote End --- I don't understand the jitter of ADC. I think the if the clock isn't beyond the maximum frenquency,the ADC can work properly.
