How to use LVDS?

Thank u Nick it's very kind of u .

and can you tell me about the follow things of your LVDS?

i wish you will succes in your project!

I think there's some confusion on the terms being used here...

LVDS is a differential I/O standard that specifies voltage levels. There is no specific form of clocking implied by using an LVDS I/O standard. Some Altera devices have native support for LVDS, while some devices require external components (resistors) to get the voltage levels right.

CDR is Clock-Data Recovery. This is a method of extracting (recovering) a clock from a data stream. At higher speeds (generally above 1.25 Gbps), the problems with controlling the relationship between a clock signal and a data signal are great enough that you really need to get the clock from the data transitions.

The scheme where you send the clock along with the data as a separate signal is often called "Clock Forwarding." Interfaces like this (SPI4.2, for example) use one or more data lines and a separate clock. For higher speeds or longer traces or more connectors, you often want to have a way to dynamically adjust the relationship between the forwarded clock and the data lines. Some of the Altera devices have the capability to do this with DPA (Dynamic Phase Alignment).

Going back to your original question, I think you were asking what Cyclone I, II, and III support relative to these terms...

Cyclone I and Cyclone II support LVDS, but only with external resisitors. Cyclone III added a true LVDS output buffer, so you don't need to use external resisitors on the transmitters. However, the resistor required on the receive side is still external for Cyclone III. If you want to use LVDS to communicate with a Cyclone device, you'll probably have to use some sort of clock-forwarding scheme.

CDR is only available in Altera's "GX" devices. There are generally fewer of these transciever channels, though they are able to run much faster than any of the more traditional I/Os (over 6 Gbps). In general, "CDR" and "Cyclone" are two terms that don't go together.

DPA is available in the newer Stratix devices (II and III).

And here's one more I'm throwing in just because I see it misused all the time and I'm on a roll here...

SERDES: This is a circuit that can take fast serial data and convert it to parallel (or vice versa). Having a SERDES does NOT imply that you have CDR. All the Stratix devices have a dedicated SERDES in some of the I/O cells. Cyclone devices use the regular logic to serialize and deserialize the I/O.

I hope that helps. I'm still not sure I answered your question, mostly because I'm not exactly sure what you were asking, but I tried.

I like thatNick noted that Cyclone III has dedicated LVDS input and output buffers now. This is a big improvement.

Cyclone I, II, III only support source synchronous LVDS -- no dedicated clock recovery circuitry. You need Stratix IIGX for CDR. This is why Nick is using clock + data for his LVDS interface with Cyclone families.

you could potentially run a very slow data rate and do oversampling, i.e. you have 100 Mbps data rate, but you run the PLL / LVDS interface on Cyclone I, II, III at 800 Mbps and get 8 sets of bit data for each 1 bit of 100 Mbps you need. You would need some period to quickly train which bit location is the best to take, some voting algorithms exist for this.

Hi All ,

I remember that Altera had a ASI / SDI development board in 2004

There were two versions of boards ,

One of them was a low cost solution , and another one was a high-en solution

The device on the low cost ASI / SDI development board was EP1C6T144C6

As there was no dedicated CDR circuitry in Cyclone I FPGA

Altera had a reference design on CDR algorithm in Cyclone I FPGA

That was a reference design doing CDR for a 270Mbps LVDS signal

(Which is a kind of over-sampling actually)

Say Data Rate = 270Mbps

Input Crystal Freq = 27MHz

Use PLL to generate a clock of 337.5MHz , we call it SCLK

Then use the PLL to generate another clock of 337.5MHz with 90 degrees phase shift

we call this clock signal sclk90

Invert this 2 clock signals ,

SCLK (0 degree phase shift)

SCLK90 (90 degree phase shift)

ISCLK (180 degree phase shift)

ISCLK90 (270 degree phase shift)

Then we sample the input data with these 4 clock signals

And finally resynchronize the data to 27MHz , the output is a 10 bit data

Virtually this is a 5 times sampling (270 x 5 / 4 = 337.5)

Is Steven talking about this kind of CDR in Low Cost FPGA ?

Hi Bland Guy ,

Thanks so much for your answer

It seems I have misunderstood CDR ...

Hello stephenzhou,

The cyclone device doesn't have CDR function, neither does stratix 1 and 2 on the LVDS port, so you should use it with reference clock. You don't need clock for each data line, and may be able to send 2bits data with one referece clock. I depends, however, on the frequency and board skew.

Thanks,