How to use LVDS?

Hi All ,

I remember that Altera had a ASI / SDI development board in 2004

There were two versions of boards ,

One of them was a low cost solution , and another one was a high-en solution

The device on the low cost ASI / SDI development board was EP1C6T144C6

As there was no dedicated CDR circuitry in Cyclone I FPGA

Altera had a reference design on CDR algorithm in Cyclone I FPGA

That was a reference design doing CDR for a 270Mbps LVDS signal

(Which is a kind of over-sampling actually)

Say Data Rate = 270Mbps

Input Crystal Freq = 27MHz

Use PLL to generate a clock of 337.5MHz , we call it SCLK

Then use the PLL to generate another clock of 337.5MHz with 90 degrees phase shift

we call this clock signal sclk90

Invert this 2 clock signals ,

SCLK (0 degree phase shift)

SCLK90 (90 degree phase shift)

ISCLK (180 degree phase shift)

ISCLK90 (270 degree phase shift)

Then we sample the input data with these 4 clock signals

And finally resynchronize the data to 27MHz , the output is a 10 bit data

Virtually this is a 5 times sampling (270 x 5 / 4 = 337.5)

Is Steven talking about this kind of CDR in Low Cost FPGA ?