I like thatNick noted that Cyclone III has dedicated LVDS input and output buffers now. This is a big improvement.
Cyclone I, II, III only support source synchronous LVDS -- no dedicated clock recovery circuitry. You need Stratix IIGX for CDR. This is why Nick is using clock + data for his LVDS interface with Cyclone families.
you could potentially run a very slow data rate and do oversampling, i.e. you have 100 Mbps data rate, but you run the PLL / LVDS interface on Cyclone I, II, III at 800 Mbps and get 8 sets of bit data for each 1 bit of 100 Mbps you need. You would need some period to quickly train which bit location is the best to take, some voting algorithms exist for this.