Forum Discussion
Honored ContributorHow to use LVDS?
in datasheet,i find maybe it isn't similar to use LVDS in Cyclone1,cyclone2,and cyclone3,
so what can i do if i want to use LVDS? 1,does it need resistor? 2,how many wire i need ? in my opinion there is two way to do this the one is two wire and use CDR, and the other is four wire use two to send data ,and two as clock reference. can you tell me the trues? thank u23 Replies
Altera_Forumi am learn lvds too , thanks your post
- Altera_Forum
The maximum voltage output differential (VOD) is increased to 600mV. The maximum VOD for ANSI specification is 450mV.
The input voltage range can be reduced to the range of 1.0V to 1.6V, 0.5V to 1.85V or 0V to 1.8V based on different frequency ranges. The ANSI/TIA/EIA-644 specification supports an input voltage range of 0V to 2.4V. -------------------------------------------------------------------------------- As above is the CIII's DC/AC Spec. I want to ask a question: If I use CIII's a receiver, it can support these Voltage? VIH=0.85V, VIL=0.5V, VID=300mV. thanks, tony - Altera_Forum
See figure 8-2 in this document on Altera's web site. It shows how to implement true LVDS with Cyclone III. http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf
- Altera_Forum
How long are your runs? It is important to make sure that the lengths of all the runs are close, otherwise signals will arrive at the destination at different times causing setup/hold problems.
- Altera_Forum
thanks very much.
- Altera_Forum
Hello stephenzhou,
The cyclone device doesn't have CDR function, neither does stratix 1 and 2 on the LVDS port, so you should use it with reference clock. You don't need clock for each data line, and may be able to send 2bits data with one referece clock. I depends, however, on the frequency and board skew. Thanks, - Altera_Forum
Hi Bland Guy ,
Thanks so much for your answer It seems I have misunderstood CDR ... - Altera_Forum
Just to be really nit-picky here, the UART-like ASI/SDI oversampling solution is not a CDR system. It does a fine job at recovering the data, but there is no clock recovered. By the time the receiver gets the data, it is running along at the local clock frequency and there is no way to recover a clock at the receiver that has a 0 ppm difference from the transmit clock.
- Altera_Forum
Hi All ,
I remember that Altera had a ASI / SDI development board in 2004 There were two versions of boards , One of them was a low cost solution , and another one was a high-en solution The device on the low cost ASI / SDI development board was EP1C6T144C6 As there was no dedicated CDR circuitry in Cyclone I FPGA Altera had a reference design on CDR algorithm in Cyclone I FPGA That was a reference design doing CDR for a 270Mbps LVDS signal (Which is a kind of over-sampling actually) Say Data Rate = 270Mbps Input Crystal Freq = 27MHz Use PLL to generate a clock of 337.5MHz , we call it SCLK Then use the PLL to generate another clock of 337.5MHz with 90 degrees phase shift we call this clock signal sclk90 Invert this 2 clock signals , SCLK (0 degree phase shift) SCLK90 (90 degree phase shift) ISCLK (180 degree phase shift) ISCLK90 (270 degree phase shift) Then we sample the input data with these 4 clock signals And finally resynchronize the data to 27MHz , the output is a 10 bit data Virtually this is a 5 times sampling (270 x 5 / 4 = 337.5) Is Steven talking about this kind of CDR in Low Cost FPGA ? - Altera_Forum
I like thatNick noted that Cyclone III has dedicated LVDS input and output buffers now. This is a big improvement.
Cyclone I, II, III only support source synchronous LVDS -- no dedicated clock recovery circuitry. You need Stratix IIGX for CDR. This is why Nick is using clock + data for his LVDS interface with Cyclone families. you could potentially run a very slow data rate and do oversampling, i.e. you have 100 Mbps data rate, but you run the PLL / LVDS interface on Cyclone I, II, III at 800 Mbps and get 8 sets of bit data for each 1 bit of 100 Mbps you need. You would need some period to quickly train which bit location is the best to take, some voting algorithms exist for this.
