How to use global clock network (Stratix)

You can use the assignment editor to place a global assignment on the net. The assignment is under logic options -> Global Signal. You can then select Global Clock as the assignment value.

Jake

Ahhh,

thanks Jake!

Now, I know what I can do with this button "Global Signal"!

Maik

Well, it seemed, as if my problem was solved, but it isn't.

One thing I have to correct: it is not a clock signal that I am generating, but a clock enable signal (verified by looking into the RTL-Viewer of my design).

So I thought I can be very clever and use "Auto Global Register Control Signals" as assignment name for my signal. After compiling my design again with this setting, I see no change at all. My generated signal still has a very high number of fan outs.

I would have expected, that the fanouts of this signal would decrease dramatically because it only has to feed the global register control line.

How can I verify that the changes I made in the assignment editor actually took place in the compiled design? And what can I do to force this assignment I made?

Thank you,

Maik

It's wrong what you expect.

The fanout will remain the same: fan out is the number of destination of your signal and count the flip flop that your signal has to reach.

Have you timing problem?

Else you don't have to worry about.

Moreover you can see if it's in the line that you want from the fitter report under resource section.

Well, maybe I have a timing problem. But I don't know exactly. That's why I am looking for the improvment of the signal speed at this special signal.

Now, that I know where to look in the Quartus II software, I am pretty sure that I am not able to let this clock enable signal use the global fast signal path.

I put this signal into the assignment editor and assigned the assignment name "Auto Global Register Control Signals" to it. After recompiling and looking into the fitter report it is not listed under "Global & Other Fast Signals". It is listed under "Non-Global High Fan-Out Signals" at position 1.

This signal I am talking about is used as chip enable in my shift register. The shift register is build out of LUTs and it is very HUUUGE (800 x 19 bits). I build this shift register out of LUTs because there are certain locations in the shift register I read from and write to during the shift process. The shifting is synchronized with the ADC clock via that enable signal I want to be global. (The ADC data is shifted through the shift register. Therefore I use the ADC clock as enable signal.) The ADC clock is derived from the main clock by dividing it by 2.

All in all, everything is working very good. However, sometimes i get some strange effect which can be caused by faulty shiftings in the shift register.

When I look at the fan outs of my ADC-clock/Shift-register-clock-enable signal, then I see that some shift register registers are reached by the enable signal in less than a ns and some others (which are far away on the FPGA) are reahed after around 5ns. This is a fact I would like to change, so that I can see if my design then will be more stable.

Maik

Imo you're looking in the wrong direction.

If you think that you've timing error internal to FPGA you have to look your timing report and analyse the path that are failing.

I've never seen problem in clk_ena signal in all my FPGA experiences, all the problems arise from bad synchronisation of the signals.

Moreover to acquire correctly your data have you used FAST INPUT REGISTER option?

You could register the 19 bit before your shift register if 1 pipe clk don't care.

Moreover you should explain better your clock scheme.

You've a main clock that is divide by 2 with a PLL and it's output is sent out to the ADC, right?

So you're ADC give you 1 sample each ADC_CLK.

Moreover with the same PLL you generate an "internal_ADC_CLK" that you use as an enable signal?

If yes it's not a very good idea, but it's better and simpler if you acquire the data with the same internal_ADC_CLK and stop.

In that way if you've some strange timing problem you can move the data you acquire shifting the ADC_CLK with the use of PLL.

But maybe I've understood not good the clock scheme you've.

It's almost correct. But I don't use a PLL to divide my master clock. I us a, well . . . , hmmm, yes I know it's bad . . . , I use a "toggle flop" to devide my master clock.

This divided clock is send directly to an FPGA pin which is connected to the ADCs clock and it is directly send to the clock enable of my shift register registers. The registers are clocked by the main clock.

"You could register the 19 bit before your shift register if 1 pipe clk don't care."-> I don't understand what you mean by that . . . . and I do not know what the FAST INPUT REGISTER option does.

From what you describe imo the clk_ena is the minor of your problem.

Have you checked the set-up and hold of your data out of the ADC?

I think that the problem is when you catch the data, not a problem in the shift register.

You need to look the data at the FPGA input with the CLK at the out of the FPGA.

FAST INPUT register is an option you can give to Quartus II telling it to use as first flip flop the one placed directly in the pin region.

Told that Imo it's better if you reverse the in ENA inside your FPGA in order to have more time to get the data.

Best thing ofc is to use the PLL so you can move the time as you want, but maybe you've some reason to not use it.