How to use global clock network (Stratix)

From what you describe imo the clk_ena is the minor of your problem.

Have you checked the set-up and hold of your data out of the ADC?

I think that the problem is when you catch the data, not a problem in the shift register.

You need to look the data at the FPGA input with the CLK at the out of the FPGA.

FAST INPUT register is an option you can give to Quartus II telling it to use as first flip flop the one placed directly in the pin region.

Told that Imo it's better if you reverse the in ENA inside your FPGA in order to have more time to get the data.

Best thing ofc is to use the PLL so you can move the time as you want, but maybe you've some reason to not use it.