How to use global clock network (Stratix)

Imo you're looking in the wrong direction.

If you think that you've timing error internal to FPGA you have to look your timing report and analyse the path that are failing.

I've never seen problem in clk_ena signal in all my FPGA experiences, all the problems arise from bad synchronisation of the signals.

Moreover to acquire correctly your data have you used FAST INPUT REGISTER option?

You could register the 19 bit before your shift register if 1 pipe clk don't care.

Moreover you should explain better your clock scheme.

You've a main clock that is divide by 2 with a PLL and it's output is sent out to the ADC, right?

So you're ADC give you 1 sample each ADC_CLK.

Moreover with the same PLL you generate an "internal_ADC_CLK" that you use as an enable signal?

If yes it's not a very good idea, but it's better and simpler if you acquire the data with the same internal_ADC_CLK and stop.

In that way if you've some strange timing problem you can move the data you acquire shifting the ADC_CLK with the use of PLL.

But maybe I've understood not good the clock scheme you've.