Honored Contributor
Honored ContributorWell, maybe I have a timing problem. But I don't know exactly. That's why I am looking for the improvment of the signal speed at this special signal.
Now, that I know where to look in the Quartus II software, I am pretty sure that I am not able to let this clock enable signal use the global fast signal path. I put this signal into the assignment editor and assigned the assignment name "Auto Global Register Control Signals" to it. After recompiling and looking into the fitter report it is not listed under "Global & Other Fast Signals". It is listed under "Non-Global High Fan-Out Signals" at position 1. This signal I am talking about is used as chip enable in my shift register. The shift register is build out of LUTs and it is very HUUUGE (800 x 19 bits). I build this shift register out of LUTs because there are certain locations in the shift register I read from and write to during the shift process. The shifting is synchronized with the ADC clock via that enable signal I want to be global. (The ADC data is shifted through the shift register. Therefore I use the ADC clock as enable signal.) The ADC clock is derived from the main clock by dividing it by 2. All in all, everything is working very good. However, sometimes i get some strange effect which can be caused by faulty shiftings in the shift register. When I look at the fan outs of my ADC-clock/Shift-register-clock-enable signal, then I see that some shift register registers are reached by the enable signal in less than a ns and some others (which are far away on the FPGA) are reahed after around 5ns. This is a fact I would like to change, so that I can see if my design then will be more stable. Maik
