How to use global clock network (Stratix)

It's almost correct. But I don't use a PLL to divide my master clock. I us a, well . . . , hmmm, yes I know it's bad . . . , I use a "toggle flop" to devide my master clock.

This divided clock is send directly to an FPGA pin which is connected to the ADCs clock and it is directly send to the clock enable of my shift register registers. The registers are clocked by the main clock.

"You could register the 19 bit before your shift register if 1 pipe clk don't care."-> I don't understand what you mean by that . . . . and I do not know what the FAST INPUT REGISTER option does.