Honored Contributor
Honored ContributorWell, it seemed, as if my problem was solved, but it isn't.
One thing I have to correct: it is not a clock signal that I am generating, but a clock enable signal (verified by looking into the RTL-Viewer of my design). So I thought I can be very clever and use "Auto Global Register Control Signals" as assignment name for my signal. After compiling my design again with this setting, I see no change at all. My generated signal still has a very high number of fan outs. I would have expected, that the fanouts of this signal would decrease dramatically because it only has to feed the global register control line. How can I verify that the changes I made in the assignment editor actually took place in the compiled design? And what can I do to force this assignment I made? Thank you, Maik
