Forum Discussion
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device?
And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...67 Replies
Altera_ForumJust now I opened FP toolbox in MAtlab 2009a but really it is diffuclt to grasp
hwo to make automatical conversion to Fixed Point? If I should do it by hand HDL testbech -- are there ready example that I would cahnge a bit for my task --how much number of lines I should wright? And I should present my work in 2-3 days so I want to present also the digital version taht i got in Simulink-- in Altera or Xilinx. The last think is very valuable there.- Altera_Forum
So what exactly do you want me to do? I can generate you the DSP model and the VHDL code from that... but you won't learn anything in the process.
- Altera_Forum
I would try to do it by myself but have no time particularly for VHDL testbench.
Untill tomorrow I would like to have the HDL realization of my simulink design to show it on my presentation -- especially it would be fine to see on Xilix, despite other options would be good. Then I will try to do it be myself. - Altera_Forum
And I also am better at least theoretically in Verilog and it is prefferable
- Altera_Forum
http://www.alteraforum.com/forum/attachment.php?attachmentid=10775&stc=1 I think if you would provide FPGA wave (signal) of this circuit it would helpful not just for me but also for those people that would see my presentation. I have said a few of them have skills in Xilings so they value it enough. Then I would by myself created the testbench for another case or in another language and produced here. It is even interesting here. Despite the image of disrete signal show me a few about nature of the sognal -- for example why all waves in this signal is the same level -- what they shows --a how display decreasing signal like in Simulink?
- Altera_Forum
Since I found this project pretty interesting, I'm going to provide you with the generated vhdl code. It is up to you to figure out how to use it, and how to build the testbench and modelsim simulation.
The code is for 1 Winner Takes All neural net with 6 inputs. If you want more than 1 winner, then you would have to regenerate the vhdl on your own. The DSP builder model is also attached. - Altera_Forum
http://www.alteraforum.com/forum/showthread.php?p=92866 http://www-mtl.mit.edu/courses/6.111/labkit/simulation.shtml -- here is about modelling testbench (despite the first item is not very understandable). Is it really automatically to make testbecnh in Verilog or at least in VHDL in ModelSim. And what WTA net you included, what is its algorithm? I need to realize my olgorithm. And one important question -- can I simulate my algorithm in Xilinx System Generator? If so -- what part of Vivaro I need to download -- as the whole bunch of 5gb is to much -- but is it possible to use just needde for HDL generated code simulation?
- Altera_Forum
The VHDL testbench is very simple to write. It's 1 file and few lines of code. Here is a guide: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
The WTA net is the same algorithm as in the simulink files set for 1 winner and 6 inputs. The VHDL code was generated using DSP builder. If you have Quartus, then you also have Altera's version of ModelSim. You just need to start a project in model sim and drop in the VHDL files and your testbench. Make sure your libraries are properly set up. I can't help you with Xilinx b/c I don't use Xilinx. This code probably won't run in with Xilinx tools b/c it is generated based on Altera's libraries. - Altera_Forum
But it is example on VHDL. It would be better to write in Verilog.
From another hand -- I was found a lot of files about Verilog testbench -- but it is not so easy to undestand despite I was theoretically accustomized in Verilog. And I do not understand why when i converted my simulink design (despite not converting in fixed point) I have got abou 6-8 thousands lines of verilog code? And if it is so simple, despite you have written otherwise above, what is rule to apply this testbench -- why clock should be apply here -- to what component of circuit it should apply--should it be once-- then what is the role of reset--shoud it apply for every "clock" when one of two different of wires go inside integrator (with minus or plus values; 0 value is final third condition when system is optimized) -- I am not very awares of these features of digital circuits. And if I pass for input such values 2,5, 7, 11, 14..what types of input I should use. Shoudl it be 4-bit as 14 is 1110, then I multilpy for 20 --should I use n-bit for 280. And of kind of output I should use --just the 1 as winner and 0 for other types? - Altera_Forum
Everything you asked has been answered in this thread, but I'll explain again:
1) Modelsim does not allow mixing of languages (on a free license), therefore since the DSP code is in VHDL, the testbench also has to be in VHDL. 2) Your conversion may be different because you were using HDL coder, while I used Altera's DSP builder. The code i got is about 1.3k lines. 3) in the testbench you set up your clock, resets and inputs: the clock I used was 500kHz. The reset is used to initialize values in synchronous processes. Since the DSP builder code is set for an active high reset, you must keep the reset high for at least 1 clock cycle, and then bring it low. The other inputs include valid, channel, and the 6 data inputs. The Valid signal is high (1) every 5 clock cycles in my design. This allows for the integrator loop to process before new data comes in. The channel input is always 0, we have 6 simultaneous inputs, no data is being multiplexed. The 6 inputs are your data. The VHDL code I provided includes the whole NN. All you need to do in connect the inputs, the clock (only 1 clock is used), and the reset and then look at the outputs. 4) My circuit is a 1 winner takes all - therefore only one of the outputs will be > 0. The inputs are set to 12 bit values. Therefore 14 is "000000001110". If you use 4 bit values, you can only input values <16. Using 12 bit you can use values <2^12
