Forum Discussion
Altera_Forum
Honored Contributor
10 years agohttp://www.alteraforum.com/forum/showthread.php?p=92866 http://www-mtl.mit.edu/courses/6.111/labkit/simulation.shtml -- here is about modelling testbench (despite the first item is not very understandable). Is it really automatically to make testbecnh in Verilog or at least in VHDL in ModelSim. And what WTA net you included, what is its algorithm? I need to realize my olgorithm. And one important question -- can I simulate my algorithm in Xilinx System Generator? If so -- what part of Vivaro I need to download -- as the whole bunch of 5gb is to much -- but is it possible to use just needde for HDL generated code simulation?