Forum Discussion
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device?
And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...67 Replies
Altera_ForumNo it is something another algorithm, probably revised.
The sorting of the inputs is the second task. Despite the first task is to show K (if 2), then 2 biggest inputs, that should be 2 outputs that is bigger than 0. So I should have N such circuits. After it I shoudl do sorting. But now I should have at least one such scheme. So it should have K outputs higher han o, and N-K outpts lower than 0 or just 0. I hoped that Fixed Point toolbox should have some automatic function to convert to fixed point, or I should do it by right click of every block and even add some additional blocks as Convert etc.- Altera_Forum
Fixed Point toolbox has some automatic capability. I don't use it, but you can google how to. It is easier to just right click individual blocks and set their data types. You should know the range of outputs each block can produce.
- Altera_Forum
Can I selct the whole scheme and aplly Fixed point toolbox? I think Matlab 2009 shuld have this capability.
I really have no time despite I am at one step to transfer my design in HDL. So it would be fine to see the hdl simulation at list in DSP, ModelSim or at the best the Xilinx. What I need for the last option? And what ranhe should I know--I have some input that has value so I need at first moment to show k biggest inouts at outputs, that should be above 0. And in my Simulink wave I see the decresing line--could I see it in HDL simulation--and what kind of wave I would see in the whole? - Altera_Forum
You should be able to apply Fixed point toolbox to the whole design. I would be careful of multiplication operations since you can reach overflow or saturation easily if you dont have enough bit width. Once you generate your HDL you can import it into Modelsim. You should also write a quick verilog testbench to simulate some inputs. Technically you should see the same waveforms in modelsim as you see in simulink if you use the same inputs.
- Altera_Forum
"if you dont have enough bit width" -- when it can happen and how to check it. What bitwidth could be of these inputs? And when this overflow and saturation happen? Ypu warn abot Gain block in multiplication -- this koeficient could be really very different from current 20 up 2000 and more.
"generate your HDL you can import it into Modelsim" and what options I also should apply for verilog file -as I have generated such file from Simulink floating points. even in Filter Design Coder. "You should also write a quick verilog testbench to simulate some inputs" -- what it means. What is Testbench --there is no HDL verifier in Matlab2009a, what is testbench (ModelSim?), and why I shoudl simulate just some inputs -- I need to use all of them -- in outputs I could use just K. If I would have enough time and Generated Fixed point Simulink could you use it in DSP Bloclset with wave results and hDL in ModelSim? - Altera_Forum
If you don't have enough bit width then your values would saturate. This means, say your range is 0 to 32, but your block wants to output 100. This would be an issue since this value is beyond the ranges that is allowable by your bit width. That means that the block would peg at 32, and will output the wrong value. You need to know what your Gain is and what values each block can output so that you can properly set your bit widths.
A testbench is a simulation file that you can write in verilog or vhdl. Here you can set up your clock, reset, and inputs. Read about writing testbenches online. The file sinmulink44_dig2009a.mdl that I attached is already configured to use the fixed point toolbox. - Altera_Forum
Yes I can use F.P.ToolBox with 2009a version but designer just with 2013.
But when I generated Verilog code by HDL Coder (or Filter) -- why and how difficult I should create testbench. Shoud I do it manually, can I exclude such file of my simulation and could I do it automatically f.e. in DSP, Model-Sim as the Xilinx System Generator has such functionality -- as seems to be. http://www.mathworks.com/help/dsp/examples/generate-hdl-code-for-programmable-fir-filter.html -- here seems no mentioning of F.P. Toolbox and Testbench And very important question -- when I choose Modelsim design files -- there is no files or the whole list that has its sub-parts what I should use if I have generated the hDL file? - Altera_Forum
- Altera_Forum
So what about HDL testbench. How difficult is it to do it manually? Could I do it automatically?
In Altera, ModelSim, DSP? System Generator seems to have. but I really have no time to download the last and is it possible to use it without Xilinx FPGA? - Altera_Forum
The HDL testbench can be made by hand. It is simply 1 file that instantiates your design, and sets up the clock, resets, inputs and outputs. If you have the basic, free, version of Modelsim all files have to be written in the same language. So DSP builder outputs VHDL, therefore you testbench has to be in VHDL. This is a pain... for me at least because I'm much better in Verilog than VHDL.
But before you do the testbench, were you able to make your HDL files from the digital version of the neural net design?
