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Altera_Forum
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10 years ago

How to simulate the FPGA neural network in Altera

I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

"if you dont have enough bit width" -- when it can happen and how to check it. What bitwidth could be of these inputs? And when this overflow and saturation happen? Ypu warn abot Gain block in multiplication -- this koeficient could be really very different from current 20 up 2000 and more.

"generate your HDL you can import it into Modelsim" and what options I also should apply for verilog file -as I have generated such file from Simulink floating points. even in Filter Design Coder.

"You should also write a quick verilog testbench to simulate some inputs" -- what it means. What is Testbench --there is no HDL verifier in Matlab2009a, what is testbench (ModelSim?), and why I shoudl simulate just some inputs -- I need to use all of them -- in outputs I could use just K.

If I would have enough time and Generated Fixed point Simulink could you use it in DSP Bloclset with wave results and hDL in ModelSim?