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Altera_Forum
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11 years ago

How to simulate the FPGA neural network in Altera

I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The HDL testbench can be made by hand. It is simply 1 file that instantiates your design, and sets up the clock, resets, inputs and outputs. If you have the basic, free, version of Modelsim all files have to be written in the same language. So DSP builder outputs VHDL, therefore you testbench has to be in VHDL. This is a pain... for me at least because I'm much better in Verilog than VHDL.

But before you do the testbench, were you able to make your HDL files from the digital version of the neural net design?