How to simulate the FPGA neural network in Altera

If you don't have enough bit width then your values would saturate. This means, say your range is 0 to 32, but your block wants to output 100. This would be an issue since this value is beyond the ranges that is allowable by your bit width. That means that the block would peg at 32, and will output the wrong value. You need to know what your Gain is and what values each block can output so that you can properly set your bit widths.

A testbench is a simulation file that you can write in verilog or vhdl. Here you can set up your clock, reset, and inputs. Read about writing testbenches online.

The file sinmulink44_dig2009a.mdl that I attached is already configured to use the fixed point toolbox.