I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device? And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...

If u are creating a new project,i believe that u already has at least a device family installed in the Quartus because u'll need to choose from the listed part numbers for the design u are creating for. If u start from a new file instead of new project, then the uninstalled device warning make more sense to me..in order for u to create a design project,compile it and open it again in future the Quartus needs to be installed with the devices. Of course the free web edition has limited feature compared to the subsciption edition.u need to check the altera software download webpage to figure out whether web edition really offers what u are trying to do.

And make sure u open a project NOT a file in the Quartus for u to able to compile the project design.

Yes I create project not file. But Create not Open. And you see this circuit in link. It could be created in Simulink and Micro-cap without any iteration--just integrator should be dependent on time. Can I realize such circuit in altera how structure and complex it could be? What main difficulties should be there?

http://postimg.org/image/m3qrcpqlj/ -- here is the logic circuit that I need to implement. At least in Micro-cap and simulink it should be done without the iterations and Neural Networks. So Could it be donhe in Altera on Verilog. What is the main difficlulties. S --comparator, there is also inverted integartor on time, that multiplies on coeficient alpha(about 1000)--so I do think it could be easier to do in Verilog then Micro-cap for example as there is no libraries for multiplier, even adder, substractor. The only difficult line is integartor..What would you suggested? Sn+2=x-A; Sn+1=x; depending on the K-Sum of Step functions An-X (intial x should be 0--but it is the main bottleneck as x begin rise on some expotential rule). And I am not aware of the fucntion of analog integrator --al other components should be analog, as the source signals should be constant.

for Example could I simply use code line "An-Amin+x" in verilog for this adder, and integrator *(-Alpha) for the node around the integartor. The fucntion of integartor is dx=x or x-A; so I do understand that x^2/2=x or x-A; or I am not correct as it is integrating for the time, but internal integral seems to be taking into account as far as I remember since mathematics. Or what such (x)=x should mean? if (x) is the derivative?

How to simulate the FPGA neural network in Altera

67 Replies

Altera_Forum
Honored Contributor
10 years ago
Oh, I understand the wave charts can just produce the signal of level of 1 or 0 so here is no nesessity to use comparator to transform the n>0 to 1 and m<=0 to 0. But is it impossible to show the decerasing for example the initial signal from 7 to 2 with almost linear decrease and then with horizonal line of final level?
Then could you explain what is the role of clock, reset? What is difference? What influence one and what the other. Which influence the integrator discrete addings (how find the integrator code in HDL generator), and what RESET reset?
Altera_Forum
Honored Contributor
10 years ago
Yes you can see the decreasing signal in the wave chart by changing the "Format" from "Literal" to "Analog". It will display a plot instead of showing actual values.

Clock is the system clock of the design. In FPGA designs everything is synchronized to the rising edge of a clock. In this case the system clock is 50kHz (20000 ns period). Then there is the "Valid" signal. This states when new data is coming in. In this design it is set to 10kHz. So every 5 clock cycles, the design logs new incoming data. This is done so that internal portions of the design (like the integrator) can complete their arithmetic loops before new data comes in. The "Reset" signal is used just initially to set everything to 0, otherwise some outputs (like multiplier outputs) can initialize with unknowns ("X") and propagate Xs through the design.

If you open up the zip file, it includes the simulink file using DSP blockset. You will see that the integrator is described using discrete blocks: a delay (z^-5), adder, multiplier, because a discrete integrator is of the form: Y(z) = T*X(z) + z^-1 * Y(z)

(I use z^-5 because sample delays refer to system clock - 50kHz - while my data rate is 10 kHz. The integrator delay in the equation above is referenced to the data delay).
Altera_Forum
Honored Contributor
10 years ago
Would you provide such introductory tutorial as https://lost-contact.mit.edu/afs/pdc.kth.se/roots/ilse/v0.7/pdc/vol/matlab/r2014b/help/hdlverifier/ug/clock-reset-and-enable-signals.html on clock, reset in general and how it works in such circuits. Are they FPGA, flip-flops? Again I needed to realize integrator in Labview (FPGA) so how would I realize such one in this module as other functions of Labview is the same as standart ones for this scheme.
Why you integrator is so compound -- T- is the time, Z-?, X(Z)?, Y(Z)?
What it means "to set everything to 0", which multiplier outputs, which unknown "X"?
Maybe that are simple questions but this field is rather unknown for me...
Altera_Forum
Honored Contributor
10 years ago
The questions you are asking me here are very fundamental. You need to have some baseline understanding of theory to know what you are doing:

1) Here is an intro to FPGAs. You can google all of this (and more) information online. http://www.tkt.cs.tut.fi/kurssit/1426/s11/lectures/tkt-1426_lect_5.pdf

2) Everything done in FPGAs is in Z - domain: http://dea.brunel.ac.uk/cmsp/home_saeed_vaseghi/chapter04-z-transform.pdf
You need to have some understanding of what a transfer function is and its properties, at least in the continuous s - domain.

3) The purpose of a reset is to easily set register states to some initial condition without recompiling the simulation. Essentially you want to define what T(0) is.

You really need to understand these concepts first before jumping into FPGAs, but we all learn as we go.
Altera_Forum
Honored Contributor
10 years ago
It is about 3 month since the last post -- but I wanted to have real understanding of this whole subject, so next set of questions. So about z-transform -- the resource is not very easygoing. What about testbench -- as it is for simulation and since I have no device -- I understand that I need to have all code for the testbench -- e.g. for the simulation? Or testbench is just a part of code and all other could be got from conversion from Simulink for example? And why testbenchis more or just for VHDL not Verilog? Next question -- I have read that in logical devices the signals could not be permanent so I understand that the RESET is for support of its constantness and clock is some signall that stimulate change in other signalls -- so what is differense between clock signal and other in and out signals as the difference even in description in schematics (arrows and circles). And the one more question -- what book or tutorial I can grasp the computer and schematic basis for vhdl and verilog as I am not from english-speaking and western european counry
Altera_Forum
Honored Contributor
10 years ago
A simulation is used to simulate "the outside world" so this couldbe switches that the user presses r signals coming from other chips. It can also be used to check the output values of your design. I think Simulink can provide a framework for the testbench, but I am not sure about that.

A reset is used to force the device into a known state, this usualy means clearing the data. The clock is used to limit the changes in data values. If you use memory this memory will require the data to be stable for a set period. By only allowing datachanges on a clock edge the data will become stable afte a while. If your design is correctly done this means all the manipulations are done before the next triggering edge. Why does the data need to be stable? Lets say a 1 is represented by 5 Volts ans a 0 by 0Vm(I don't think these are the values used in an FPGA). If you change from one to the other this takes time (slew rate). So what value should be assigned to a 2.5 volt signal? In practice ranges are defined so a 1 is everything between 5 and 3 volt and a 0 is assigned to everything between 2 and 0. But you will always have that small undefined gap. A clock is used to prevent the value from bei g mid-transition when read by a memory element.

As for information on VHDL or Verilog, search the forum for books. There are enouh threads that provide infor ation on good ones. One of them: http://www.alteraforum.com/forum/showthread.php?t=41998&highlight=books+vhdl

i don't know any good books in a language other than english.
(http://www.alteraforum.com/forum/showthread.php?t=41998&highlight=books+vhdl)
Altera_Forum
Honored Contributor
10 years ago
I need exactly "english" books but not for vhdl or verilog as there are a lot of them but on hardware for this languages. I have basic understanding of this from "shematechnics" in russian-speaking literature but it differetiate from the english terminology and practice. So I need books (about such of 200 pages) with brief but enough explanations, without to be too inclusive but also not too superficial

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How to simulate the FPGA neural network in Altera

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