How to get 45Mhz clock out?

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Why not use clken at 45MHz using clock 100MHz as system clock, if it is for inside fpga processing?

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How do you make a clockenable of 45 MHz starting from a 100 MHz clock? Catch 22?

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In fact, I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz.

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I just tried on a blank project and it worked perfectly. Is 45MHz the only output? Because as joysb says if you have other output frequencies it can make it impossible for the pll in some cases.

Why not use clken at 45MHz using clock 100MHz as system clock, if it is for inside fpga processing?

If it is for outside fpga you can try 90MHz or 180 ...etc and divide internally then use ddr to pass 45 out

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I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz.

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Basically 100MHz input and 45 MHz does work. But, the LCM (Least Common Multiple) of the input clock and all output clocks must be in the range of the PLL's VCO, e.g. at 100MHz input, and outputs of 45MHz and 80MHz the VCO needs to run at 3.6 GHz, where the allowable range only is 600 to 1400 MHz.

Hi guys:

In fact, I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz.

Thanks

Jerry

use megafunction wizard.

[tools] -> [megawizard plug-in manager]

[create a new custom megafunction variation] -> [Next]

[I/O] -> [ALTPLL]