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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz. --- Quote End --- Basically 100MHz input and 45 MHz does work. But, the LCM (Least Common Multiple) of the input clock and all output clocks must be in the range of the PLL's VCO, e.g. at 100MHz input, and outputs of 45MHz and 80MHz the VCO needs to run at 3.6 GHz, where the allowable range only is 600 to 1400 MHz.
