how to generate a reset signal in Altera Cyclone Ⅳ series?

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All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

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True, if you use the default. You can set them to any value you want using initialization (at least in Verilog, I assume VHDL is similar). Quartus understands that if initialize a register to '1' it will invert the logic sense (since the register will physically initialize to a '0'). So to you it looks like the register initializes to a '1' but it is implemented as active low logic in Quartus (ie, '1' = low level, '0' = high level).

I use the following Verilog to generate a long reset pulse at powerup in my Altera FPGA:

   // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
`ifdef SIMULATION
    reg          pup_count = 25'd24999900;
`else
    reg          pup_count = 25'd0;
`endif
    reg         pup_reset = 1'b1;
    always @(posedge CLOCK_50)
    begin
    pup_count <=# TPD pup_count + 1'd1;
    if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
    end
    wire         reset = pup_reset;

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True, if you use the default. You can set them to any value you want using initialization (at least in Verilog, I assume VHDL is similar).

I use the following Verilog to generate a long reset pulse at powerup in my Altera FPGA:

   // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
`ifdef SIMULATION
    reg  		pup_count = 25'd24999900;
`else
    reg  		pup_count = 25'd0;
`endif
    reg 		pup_reset = 1'b1;
    always @(posedge CLOCK_50)
	begin
	pup_count <=# TPD pup_count + 1'd1;
	if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
	end
    wire 		reset = pup_reset;

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But there are no other reset instructions in my program

only one reset instruction is

input reset;

reg[10:0] counting;

always@(posedge clk or negedge reset)

begin

if(!reset)

counting <= 11'd1;

end

counting is actually equal to 1 after power on, why?

The M1 pin is configured as reset pin. This pin is routed to some logic cell in the FPGA which contains a flip-flop/register.

If it is asynchronous reset, it will be routed to the asynchronous reset port of the registers in that logic cell. If synchronous, it will be ANDed with register inputs.

Now:

When the FPGA powers up, all internal values of all registers, flip-flops, look-up tables, etc are zero. This is the case for the reset signal in that logic cell; thus your logic remains reset until FPGA powers up successfully. In this case the counting signal should be zero at first, and then gets 11'd1. You may not be able to see the 11'd0 value in the SignalTap since FPGA may not be alive at that moments, but you should test it. I'm not sure about this point.

After power up, the value which is driven from the reset circuit outside FPGA supplies the reset signal in the FPGA logic cell. Depending on your external value the reset signal inside FPGA may be zero or one.

So, at power up your reset signal is zero and then it will be driven by the external value.

BUT, the reset signal may fluctuate a number of times before your design becomes stable, so use a reset synchroniser similar to what I posted in order to remove all glitches on the reset signal, both from sources inside FPGA and glitches outside FPGA due to reset circuit (a micro-switch probably).

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When the FPGA powers up, all internal values of all registers, flip-flops, look-up tables, etc are zero.

This is the case for the reset signal in that logic cell;

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An alternative that could be considered would be assigning an inverted logic straight to the I/O.

I'm not sure of that, but perhaps the option FAST_OUTPUT_REGISTER is likely to implement that functionality.

It is uposed to bypass the register.

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The M1 pin is configured as reset pin. This pin is routed to some logic cell in the FPGA which contains a flip-flop/register.

If it is asynchronous reset, it will be routed to the asynchronous reset port of the registers in that logic cell. If synchronous, it will be ANDed with register inputs.

Now:

When the FPGA powers up, all internal values of all registers, flip-flops, look-up tables, etc are zero. This is the case for the reset signal in that logic cell; thus your logic remains reset until FPGA powers up successfully. In this case the counting signal should be zero at first, and then gets 11'd1. You may not be able to see the 11'd0 value in the SignalTap since FPGA may not be alive at that moments, but you should test it. I'm not sure about this point.

After power up, the value which is driven from the reset circuit outside FPGA supplies the reset signal in the FPGA logic cell. Depending on your external value the reset signal inside FPGA may be zero or one.

So, at power up your reset signal is zero and then it will be driven by the external value.

BUT, the reset signal may fluctuate a number of times before your design becomes stable, so use a reset synchroniser similar to what I posted in order to remove all glitches on the reset signal, both from sources inside FPGA and glitches outside FPGA due to reset circuit (a micro-switch probably).

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thank you for your reply,there is no reset circuit outside.

like you said"In this case the counting signal should be zero at first, and then gets 11'd1."

I am a newbie, I'm sorry i don't know what you mean.