how to generate a reset signal in Altera Cyclone Ⅳ series?

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All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

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True, if you use the default. You can set them to any value you want using initialization (at least in Verilog, I assume VHDL is similar). Quartus understands that if initialize a register to '1' it will invert the logic sense (since the register will physically initialize to a '0'). So to you it looks like the register initializes to a '1' but it is implemented as active low logic in Quartus (ie, '1' = low level, '0' = high level).

I use the following Verilog to generate a long reset pulse at powerup in my Altera FPGA:

   // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
`ifdef SIMULATION
    reg          pup_count = 25'd24999900;
`else
    reg          pup_count = 25'd0;
`endif
    reg         pup_reset = 1'b1;
    always @(posedge CLOCK_50)
    begin
    pup_count <=# TPD pup_count + 1'd1;
    if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
    end
    wire         reset = pup_reset;