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The M1 pin is configured as reset pin. This pin is routed to some logic cell in the FPGA which contains a flip-flop/register.
If it is asynchronous reset, it will be routed to the asynchronous reset port of the registers in that logic cell. If synchronous, it will be ANDed with register inputs.
Now:
When the FPGA powers up, all internal values of all registers, flip-flops, look-up tables, etc are zero. This is the case for the reset signal in that logic cell; thus your logic remains reset until FPGA powers up successfully. In this case the counting signal should be zero at first, and then gets 11'd1. You may not be able to see the 11'd0 value in the SignalTap since FPGA may not be alive at that moments, but you should test it. I'm not sure about this point.
After power up, the value which is driven from the reset circuit outside FPGA supplies the reset signal in the FPGA logic cell. Depending on your external value the reset signal inside FPGA may be zero or one.
So, at power up your reset signal is zero and then it will be driven by the external value.
BUT, the reset signal may fluctuate a number of times before your design becomes stable, so use a reset synchroniser similar to what I posted in order to remove all glitches on the reset signal, both from sources inside FPGA and glitches outside FPGA due to reset circuit (a micro-switch probably).
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thank you for your reply,there is no reset circuit outside.
like you said"In this case the counting signal should be zero at first, and then gets 11'd1."
I am a newbie, I'm sorry i don't know what you mean.
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