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Honored Contributor
Honored Contributorhow to generate a reset signal in Altera Cyclone Ⅳ series?
Verilog:
input reset;
reg counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd0;
end reset signal is connect to “M1” pin. is it counting =...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- When the FPGA powers up, all internal values of all registers, flip-flops, look-up tables, etc are zero. This is the case for the reset signal in that logic cell; --- Quote End --- An alternative that could be considered would be assigning an inverted logic straight to the I/O. I'm not sure of that, but perhaps the option FAST_OUTPUT_REGISTER is likely to implement that functionality. It is uposed to bypass the register.
