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True, if you use the default. You can set them to any value you want using initialization (at least in Verilog, I assume VHDL is similar).
I use the following Verilog to generate a long reset pulse at powerup in my Altera FPGA:
// PowerUP Reset Logic
// generate a 500ms reset pulse on initial powerup
`ifdef SIMULATION
reg pup_count = 25'd24999900;
`else
reg pup_count = 25'd0;
`endif
reg pup_reset = 1'b1;
always @(posedge CLOCK_50)
begin
pup_count <=# TPD pup_count + 1'd1;
if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
end
wire reset = pup_reset;
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But there are no other reset instructions in my program
only one reset instruction is
input reset;
reg[10:0] counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd1;
end
counting is actually equal to 1 after power on, why?
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