how to generate a reset signal in Altera Cyclone Ⅳ series?

Yes, but it will not increase and remains zero permanently.

Try this:

    input reset;
    reg counting;
    reg r_reset_n;
    always@(posedge clk or negedge reset)
    begin
        if(!reset)
            begin
                counting <= 11'd0;
                r_reset_n <= 1'b0;
            end
        else
            if (counting <= 11'd1234)// replace 11'd1234 with required reset delay, based on clock frequency, in order to remove glitches.
                begin
                    counting <= counting + 1'b1;
                    r_reset_n <= 1'b0;
                end
            else
                begin
                    counting <= 11'd2047;
                    r_reset_n <= 1'b1;
                end
    end

hello

when there is a falling edge of reset signal,counting will equal to 0.

but my question is Could "M1" pin will generate a falling edge when FPGA board power on?

--- Quote Start ---

Yes, but it will not increase and remains zero permanently.

Try this:

    input reset;
    reg counting;
    reg r_reset_n;
    always@(posedge clk or negedge reset)
    begin
        if(!reset)
            begin
                counting <= 11'd0;
                r_reset_n <= 1'b0;
            end
        else
            if (counting <= 11'd1234)// replace 11'd1234 with required reset delay, based on clock frequency, in order to remove glitches.
                begin
                    counting <= counting + 1'b1;
                    r_reset_n <= 1'b0;
                end
            else
                begin
                    counting <= 11'd2047;
                    r_reset_n <= 1'b1;
                end
    end

--- Quote End ---

hello

when there is a falling edge of reset signal,counting will equal to 0.

but my question is Could "M1" pin will generate a falling edge when FPGA board power on?

--- Quote Start ---

but my question is Could "M1" pin will generate a falling edge when FPGA board power on?

--- Quote End ---

All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

--- Quote Start ---

All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

--- Quote End ---

 input reset;
 reg counting;
 
 always@(posedge clk or negedge reset)
  begin
   if(!reset)
    counting <= 11'd1;
  end

I found that it counting is equal to 1 after power up! why?

According to your post "M1" is input, not output.

If you mean that another pin could generate falling edge at power up, No.

--- Quote Start ---

According to your post "M1" is input, not output.

If you mean that another pin could generate falling edge at power up, No.

--- Quote End ---

I used "counting <= 11'd1" to replace "counting <= 11'd0"

after power on, Counting is actually equal to 1, I want to konw where this “reset” falling edge come from?

this reset signal is connected to FPGA's “M1” pin. is it from FPGA device?

--- Quote Start ---

All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

--- Quote End ---

but i uesd "counting <= 11'd1" to replace "counting <= 11'd0"

after power on, Counting is actually equal to 1, why?

--- Quote Start ---

but i uesd "counting <= 11'd1" to replace "counting <= 11'd0"

after power on, Counting is actually equal to 1, why?

--- Quote End ---

You've not posted any code with the instruction "counting <= 11'd1".

Why not just try using the exact code msj posted on# 2 ?

--- Quote Start ---

You've not posted any code with the instruction "counting <= 11'd1".

Why not just try using the exact code msj posted on# 2 ?

--- Quote End ---

input reset;
 reg counting;
 
 always@(posedge clk or negedge reset)
  begin
   if(!reset)
    counting <= 11'd1;
  end

I had been modify.

counting is equal to 1 after power on.