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Honored Contributor
Honored Contributorhow to generate a reset signal in Altera Cyclone Ⅳ series?
Verilog:
input reset;
reg counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd0;
end reset signal is connect to “M1” pin. is it counting =...
Altera_ForumHonored Contributor
Honored ContributorAccording to your post "M1" is input, not output.
If you mean that another pin could generate falling edge at power up, No.
