Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhow to generate a reset signal in Altera Cyclone Ⅳ series?
Verilog:
input reset;
reg counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd0;
end reset signal is connect to “M1” pin. is it counting =...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic. --- Quote End ---
input reset;
reg counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd1;
end
