Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

how to generate a reset signal in Altera Cyclone Ⅳ series?

Verilog: input reset; reg counting; always@(posedge clk or negedge reset) begin if(!reset) counting <= 11'd0; end reset signal is connect to “M1” pin. is it counting =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

All initial states of variables in Altera FPGA devices after power up are set to 'zero' logic.

--- Quote End --- 

 input reset;
 reg counting;
 
 always@(posedge clk or negedge reset)
  begin
   if(!reset)
    counting <= 11'd1;
  end

I found that it counting is equal to 1 after power up! why?